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IC41SV4105
Document Title
1Mx4 bit Dynamic RAM with Fast Page Mode
Revision History
Revision No
0A
History
Initial Draft
Draft Date
October 29,2001
Remark
Preliminary
The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices.
Integrated Circuit Solution Inc.
DR032-0A 10/29/2001
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IC41SV4105
Preliminary
1M x 4 (4-MBIT) DYNAMIC RAM WITH FAST PAGE MODE
FEATURES
* Fast Page Mode Access Cycle * TTL compatible inputs and outputs * Refresh Interval: -- 1,024 cycles/16 ms * Refresh Mode: RAS-Only, CAS-before-RAS (CBR), and Hidden * JEDEC standard pinout * Single power supply: 1.9V - 2.4V
DESCRIPTION
The ICSI 4105 Series is a 1,048,576 x 4-bit high-performance CMOS Dynamic Random Access Memory. The Fast Page Mode allows 1,024 random accesses within a single row with access cycle time as short as 20 ns per 4-bit word. These features make the 4105 Series ideally suited for digital signal processing, and low power portable audio applications. The 4105 Series is packaged in a 20-pin 300mil SOJ and a 20 pin TSOP-2
KEY TIMING PARAMETERS
Parameter
RAS Access Time (tRAC) CAS Access Time (tCAC) Column Address Access Time (tAA) Fast Page Mode Cycle Time (tPC) Read/Write Cycle Time (tRC) -50 50 14 25 20 90 -70 -100 Unit 70 20 35 45 130 100 25 50 60 180 ns ns ns ns ns
PIN CONFIGURATION 20 (26) Pin SOJ, TSOP-2
I/O0 I/O1 WE RAS A9 1 2 3 4 5 26 25 24 23 22 GND I/O3 I/O2 CAS OE
PIN DESCRIPTIONS
A0-A9 I/O0-3 WE OE RAS CAS Vcc Address Inputs Data Inputs/Outputs Write Enable Output Enable Row Address Strobe Column Address Strobe Power Ground
A0 A1 A2 A3 VCC
9 10 11 12 13
18 17 16 15 14
A8 A7 A6 A5 A4
GND
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. (c) Copyright 2000, Integrated Circuit Solution Inc.
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Integrated Circuit Solution Inc.
DR032-0A 10/29/2001
IC41SV4105
FUNCTIONAL BLOCK DIAGRAM
OE WE CAS CONTROL LOGIC WE CONTROL LOGICS OE CONTROL LOGIC
CAS
CAS
WE
OE
RAS
RAS CLOCK GENERATOR
DATA I/O BUS
REFRESH COUNTER
DATA I/O BUFFERS
ROW DECODER
RAS
COLUMN DECODERS SENSE AMPLIFIERS
I/O0-I/O3
MEMORY ARRAY 1,048,576 x 4
ADDRESS BUFFERS A0-A9
TRUTH TABLE
Function Standby Read Write: Word (Early Write) Read-Write Hidden Refresh RAS-Only Refresh CBR Refresh
Note: 1. EARLY WRITE only.
Read Write(1)
RAS H L L L LHL LHL L HL
CAS H L L L L L H L
WE X H L HL H L X X
OE X L X LH L X X X
Address tR/tC X ROW/COL ROW/COL ROW/COL ROW/COL ROW/COL ROW/NA X
I/O High-Z DOUT DIN DOUT, DIN DOUT DIN High-Z High-Z
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IC41SV4105
Functional Description
The IC41SV4105 are CMOS DRAMs optimized for highspeed bandwidth, low power applications. During READ or WRITE cycles, each bit is uniquely addressed through the 10 address bits. These are entered 10 bits (A0-A9) at a time. The row address is latched by the Row Address Strobe (RAS). The column address is latched by the Column Address Strobe (CAS). RAS is used to latch the first ten bits and CAS is used the latter ten bits.
Refresh Cycle
To retain data, 1,024 refresh cycles are required in each 16 ms period . There are two ways to refresh the memory: 1. By clocking each of the 1,024 row addresses (A0 through A9) with RAS at least once every 16 ms . Any read, write, read-modify-write or RAS-only cycle refreshes the addressed row. 2. Using a CAS-before-RAS refresh cycle. CAS-beforeRAS refresh is activated by the falling edge of RAS, while holding CAS LOW. In CAS-before-RAS refresh cycle, an internal 10-bit counter provides the row addresses and the external address inputs are ignored. CAS-before-RAS is a refresh-only mode and no data access or device selection is allowed. Thus, the output remains in the High-Z state during the cycle.
Memory Cycle
A memory cycle is initiated by bring RAS LOW and it is terminated by returning both RAS and CAS HIGH. To ensures proper device operation and data integrity any memory cycle, once initiated, must not be ended or aborted before the minimum tRAS time has expired. A new cycle must not be initiated until the minimum precharge time tRP, tCP has elapsed.
Power-On
After application of the VCC supply, an initial pause of 200 s is required followed by a minimum of eight initialization cycles (any combination of cycles containing a RAS signal). During power-on, it is recommended that RAS track with VCC or be held at a valid VIH to avoid current surges.
Read Cycle
A read cycle is initiated by the falling edge of CAS or OE, whichever occurs last, while holding WE HIGH. The column address must be held for a minimum time specified by tAR. Data Out becomes valid only when tRAC, tAA, tCAC and tOE are all satisfied. As a result, the access time is dependent on the timing relationships between these parameters.
Write Cycle
A write cycle is initiated by the falling edge of CAS and WE, whichever occurs last. The input data must be valid at or before the falling edge of CAS or WE, whichever occurs last.
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IC41SV4105
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VT VCC IOUT PD TA TSTG Parameters Voltage on Any Pin Relative to GND Supply Voltage Output Current Power Dissipation Commercial Operation Temperature Storage Temperature Rating -0.5 to +2.6 -0.5 to +2.6 50 0.2 0 to +70 -55 to +125 Unit V V mA W o C o C
Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED OPERATING CONDITIONS (Voltages are referenced to GND.)
Symbol VCC VIH VIL TA Parameter Supply Voltage Input High Voltage Input Low Voltage Commercial Ambient Temperature Min. 1.9 1.4 -0.3 0 Typ. 2.2 - - - Max. 2.4 VCC + 0.3 0.6 70 Unit V V V
o
C
CAPACITANCE(1,2)
Symbol CIN1 CIN2 CIO Parameter Input Capacitance: A0-A9 Input Capacitance: RAS, CAS, WE, OE Data Input/Output Capacitance: I/O0-I/O3 Max. 5 7 7 Unit pF pF pF
Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25oC, f = 1 MHz.
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IC41SV4105
ELECTRICAL CHARACTERISTICS(1)
(Recommended Operating Conditions unless otherwise noted.) Symbol Parameter IIL IIO VOH VOL ICC1 ICC2 ICC3 Input Leakage Current Output Leakage Current Output High Voltage Level Output Low Voltage Level Standby Current: TTL Standby Current: CMOS Operating Current: Random Read/Write(2,3,4) Average Power Supply Current Operating Current: Fast Page Mode(2,3,4) Average Power Supply Current Refresh Current: RAS-Only(2,3) Average Power Supply Current Refresh Current: CBR(2,3,5) Average Power Supply Current Test Condition Any input 0V VIN Vcc Other inputs not under test = 0V Output is disabled (Hi-Z) 0V VOUT Vcc IOH = -2.0 mA IOL = 2 mA RAS, CAS VIH RAS, CAS VCC - 0.2V RAS, CAS, Address Cycling, tRC = tRC (min.) RAS = VIL, CAS VIH tRC = tRC (min.) RAS Cycling, CAS VIH tRC = tRC (min.) RAS, CAS Cycling tRC = tRC (min.) -50 -70 -100 -50 -70 -100 -50 -70 -100 -50 -70 -100 - - - - - - - - - - - - Speed Min. -5 -5 1.6 - - Max. 5 5 - 0.8 1 0.5 70 60 50 55 45 35 70 60 50 70 60 50 Unit A A V V mA mA mA
ICC4
mA
ICC5
mA
ICC6
mA
Notes: 1. An initial pause of 200 s is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper device operation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded. 2. Dependent on cycle rates. 3. Specified values are obtained with minimum cycle time and the output open. 4. Column-address is changed once each Fast page cycle. 5. Enables on-chip refresh and address counters.
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IC41SV4105
AC CHARACTERISTICS(1,2,3,4,5,6)
(Recommended Operating Conditions unless otherwise noted.) -50 Symbol tRC tRAC tCAC tAA tRAS tRP tCAS tCP tCSH tRCD tASR tRAH tASC tCAH tAR tRAD tRAL tRPC tRSH tCLZ tCRP tOD tOE tOES tRCS tRRH tRCH tWCH tWCR tWP tRWL tCWL tWCS tDHR Parameter Random READ or WRITE Cycle Time Access Time from RAS(6, 7) Access Time from CAS(6, 8, 15) Access Time from Column-Address(6) RAS Pulse Width RAS Precharge Time CAS Pulse Width(23) CAS Precharge Time(9) CAS Hold Time (21) RAS to CAS Delay Time(10, 20) Row-Address Setup Time Row-Address Hold Time Column-Address Setup Time(20) Column-Address Hold Time(20) Column-Address Hold Time (referenced to RAS) RAS to Column-Address Delay Time(11) Column-Address to RAS Lead Time RAS to CAS Precharge Time RAS Hold Time CAS to Output in Low-Z(15, 24) CAS to RAS Precharge Time(21) Output Disable Time(19, 24) Output Enable Time(15, 16) OE LOW to CAS HIGH Setup Time Read Command Setup Time(17, 20) Read Command Hold Time (referenced to RAS)(12) Read Command Hold Time (referenced to CAS)(12, 17, 21) Write Command Hold Time(17) Write Command Hold Time (referenced to RAS)(17) Write Command Pulse Width(17) Write Command to RAS Lead Time(17) Write Command to CAS Lead Time(17, 21) Write Command Setup Time(14, 17, 20) Data-in Hold Time (referenced to RAS) Min. 90 - - - 50 30 8 8 50 19 0 8 0 8 40 14 25 0 14 3 5 3 - 5 0 0 0 8 40 8 14 14 0 40 Max. - 50 14 25 10K - 10K - - 36 - - - - - 25 - - - - - 15 15 - - - - - - - - - - - -70 Min. Max. 130 - - - 70 50 20 10 70 20 0 10 0 15 70 15 35 5 20 3 5 3 5 0 0 0 10 70 10 20 20 0 50 - 70 20 35 10K - 10K - - 50 - - - - - 35 - - - - - 20 20 - - - - - - - - - - - -100 Min. Max. Units 180 - - - 100 70 25 10 100 25 0 15 0 20 100 20 50 5 25 3 5 3 5 0 0 0 15 100 15 25 25 0 60 - 100 25 50 10K - 10K - - 75 - - - - - 50 - - - - - 25 25 - - - - - - - - - - - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Integrated Circuit Solution Inc.
DR032-0A 10/29/2001
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IC41SV4105
AC CHARACTERISTICS (Continued)(1,2,3,4,5,6)
(Recommended Operating Conditions unless otherwise noted.) Symbol tACH tOEH tDS tDH tRWC tRWD tCWD tAWD tPC tRASP tCPA tPRWC tOFF tCSR tCHR tORD tREF tT Parameter Column-Address Setup Time to CAS Precharge during WRITE Cycle OE Hold Time from WE during READ-MODIFY-WRITE cycle(18) Data-In Setup Time(15, 22) Data-In Hold Time(15, 22) READ-MODIFY-WRITE Cycle Time RAS to WE Delay Time during READ-MODIFY-WRITE Cycle(14) CAS to WE Delay Time(14, 20) Column-Address to WE Delay Time(14) Fast Page Mode READ or WRITE Cycle Time Fast Page Mode RAS Pulse Width Access Time from CAS Precharge(15) Fast Page Mode READ WRITE Cycle Time Output Buffer Turn-Off Delay from CAS or RAS(13,15,19, 24) CAS Setup Time (CBR REFRESH)(20, 25) CAS Hold Time (CBR REFRESH)( 21, 25) OE Setup Time prior to RAS during HIDDEN REFRESH Cycle Auto Refresh Period 1,024 Cycles Transition Time (Rise or Fall)(2, 3) Min. 15 10 0 8 125 70 34 42 20 50 47 3 5 10 0 - 3 -50 Max. - - - - - - - - - 100K 27 - 15 - - - 16 50 -70 Min. Max. 15 20 0 15 185 100 45 60 45 70 100 3 5 10 0 - 3 - - - - - - - - - 100K 40 - 15 - - - 16 50 -100 Min. Max. 15 25 0 20 240 130 55 85 60 100 120 3 5 10 0 - 3 - - - - - - - - - 100K 55 - 15 - - - 16 50 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns
AC TEST CONDITIONS
Output load: One TTL Load and 100 pF
Input timing reference levels:
VIH = 1.4V, VIL = 0.6V
Output timing reference levels: VOH = 1.4V, VOL = 0.6V
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Integrated Circuit Solution Inc.
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IC41SV4105
Notes: 1. An initial pause of 200 s is required after power-up followed by eight RAS refresh cycle (RAS-Only or CBR) before proper device operation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded. 2. VIH (MIN) and VIL (MAX) are reference levels for measuring timing of input signals. Transition times, are measured between VIH and VIL (or between VIL and VIH) and assume to be 1 ns for all inputs. 3. In addition to meeting the transition rate specification, all input signals must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner. 4. If CAS and RAS = VIH, data output is High-Z. 5. If CAS = VIL, data output may contain data from the last valid READ cycle. 6. Measured with a load equivalent to one TTL gate and 100 pF. 7. Assumes that tRCD tRCD (MAX). If tRCD is greater than the maximum recommended value shown in this table, tRAC will increase by the amount that tRCD exceeds the value shown. 8. Assumes that tRCD tRCD (MAX). 9. If CAS is LOW at the falling edge of RAS, data out will be maintained from the previous cycle. To initiate a new cycle and clear the data output buffer, CAS and RAS must be pulsed for tCP. 10. Operation with the tRCD (MAX) limit ensures that tRAC (MAX) can be met. tRCD (MAX) is specified as a reference point only; if tRCD is greater than the specified tRCD (MAX) limit, access time is controlled exclusively by tCAC. 11. Operation within the tRAD (MAX) limit ensures that tRCD (MAX) can be met. tRAD (MAX) is specified as a reference point only; if tRAD is greater than the specified tRAD (MAX) limit, access time is controlled exclusively by tAA. 12. Either tRCH or tRRH must be satisfied for a READ cycle. 13. tOFF (MAX) defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL. 14. tWCS, tRWD, tAWD and tCWD are restrictive operating parameters in LATE WRITE and READ-MODIFY-WRITE cycle only. If tWCS tWCS (MIN), the cycle is an EARLY WRITE cycle and the data output will remain open circuit throughout the entire cycle. If tRWD tRWD (MIN), tAWD tAWD (MIN) and tCWD tCWD (MIN), the cycle is a READ-WRITE cycle and the data output will contain data read from the selected cell. If neither of the above conditions is met, the state of I/O (at access time and until CAS and RAS or OE go back to VIH) is indeterminate. OE held HIGH and WE taken LOW after CAS goes LOW result in a LATE WRITE (OE-controlled) cycle. 15. Output parameter (I/O) is referenced to corresponding CAS input. 16. During a READ cycle, if OE is LOW then taken HIGH before CAS goes HIGH, I/O goes open. If OE is tied permanently LOW, a LATE WRITE or READ-MODIFY-WRITE is not possible. 17. Write command is defined as WE going low. 18. LATE WRITE and READ-MODIFY-WRITE cycles must have both tOD and tOEH met (OE HIGH during WRITE cycle) in order to ensure that the output buffers will be open during the WRITE cycle. The I/Os will provide the previously written data if CAS remains LOW and OE is taken back to LOW after tOEH is met. 19. The I/Os are in open during READ cycles once tOD or tOFF occur. 20. Determined by falling edge of CAS. 21. Determined by rising edge of CAS. 22. These parameters are referenced to CAS leading edge in EARLY WRITE cycles and WE leading edge in LATE WRITE or READMODIFY-WRITE cycles. 23. CAS must meet minimum pulse width. 24. The 3 ns minimum is a parameter guaranteed by design. 25. Enables on-chip refresh and address counters.
Integrated Circuit Solution Inc.
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IC41SV4105
READ CYCLE
tRC tRAS tRP
RAS
tCSH tCRP tRCD tRSH tCAS tRRH
CAS
tAR tASR tRAD tRAH tRAL tASC tCAH
ADDRESS WE
Row
tRCS
Column
tRCH
Row
tAA tRAC tCAC tCLZ
tOFF(1)
I/O
Open
tOE
Valid Data
tOD
Open
OE
tOES
Don't Care
Note: 1. tOFF is referenced from rising edge of RAS or CAS, whichever occurs last.
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Integrated Circuit Solution Inc.
DR032-0A 10/29/2001
IC41SV4105
READ WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE Cycles)
tRWC tRAS
tRP
RAS
tCSH tCRP tRCD tRSH tCAS
CAS
tAR tASR tRAD tRAH tRAL tASC tCAH tACH
ADDRESS
Row
tRCS
Column
tRWD tCWD tAWD
Row
tCWL tRWL tWP
WE
tAA tRAC tCAC tCLZ tDS tDH
I/O
Open
tOE
Valid DOUT
tOD
Valid DIN
Open
tOEH
OE
Don't Care
Integrated Circuit Solution Inc.
DR032-0A 10/29/2001
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IC41SV4105
EARLY WRITE CYCLE (OE = DON'T CARE)
tRC tRAS tRP
RAS
tCSH tCRP tRCD tRSH tCAS
CAS
tAR tASR tRAD tRAH tASC tRAL tCAH tACH
ADDRESS
Row
Column
tCWL tRWL tWCR tWCS tWCH tWP
Row
WE
tDHR tDS tDH
I/O
Valid Data
Don't Care
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IC41SV4105
FAST PAGE MODE READ CYCLE
tRASP
tRP
RAS
tCSH tCAS tCRP tRCD tCP tCAS tCP tPC tRSH tCAS tCRP
CAS
tAR tRAL tRAH tASR tRAD tASC tCAH tASC tAR tCAH tASC tCAH
ADDRESS
Row
Column
Column
Column
tRCS
WE
tAA tCAC tOE tCPA tAA tCAC tOE tCPA tAA tCAC tOE
OE
tRAC tCLZ
tOD tCLZ
OUT OUT
tOD tCLZ
OUT
tOD
I/O
Don't Care
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IC41SV4105
FAST PAGE MODE EARLY WRITE CYCLE
tRASP
tRP
RAS
tCSH tCAS tCRP tRCD tCP tPC tCAS tCP tRSH tCAS tCRP
CAS
tAR tRAL tRAH tASR tRAD tASC tCAH tASC tAR tCWL tWCS tWP tWCH tWCS tWP tCAH tASC tCAH
ADDRESS
Row
Column
Column
tCWL tWCH tWCS
Column
tRWL tWCH tWP
WE
tWCR
OE
tDHR tDS tDH tDS tDH tDS tDH
I/O
Valid DIN
Valid DIN
Valid DIN
Don't Care
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Integrated Circuit Solution Inc.
DR032-0A 10/29/2001
IC41SV4105
FAST PAGE MODE READ WRITE CYCLE (LATE WRITE AND READ-MODIFY-WRITE CYCLE)
tRASP tRP
RAS
tCSH tCAS tCRP tRCD tCP tPRWC tCAS tCP tRSH tCAS tCRP
CAS
tAR tRAL tRAH tASR tRAD tASC tCAH tASC tAR tCWL tRWD tAWD tCWD tCAH tASC tCAH
ADDRESS
Row
Column
Column
tCWL tAWD tCWD
Column
tCWL tRWL tWP tAWD tCWD
tRCS
tWP
tWP
WE
tAA tCAC tOE tCAC tOE tAA tCAC tOE tAA
OE
tOD tRAC tCLZ tDH tDS tCLZ
OUT IN OUT IN
tOD tDH tDS tCLZ
OUT
tOD tDH tDS
IN
I/O
Don't Care
RAS-ONLY REFRESH CYCLE (OE, WE = DON'T CARE) RAS
tRC tRAS tRP
RAS
tCRP tRPC
CAS
tASR tRAH
ADDRESS I/O
Row Open
Row
Don't Care
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DR032-0A 10/29/2001
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IC41SV4105
CBR REFRESH CYCLE (Addresses; WE, OE = DON'T CARE)
tRP
tRAS
tRP
tRAS
RAS
tRPC tCP tCHR tCSR tRPC tCSR tCHR
CAS I/O Open
Don't Care
HIDDEN REFRESH CYCLE(1) (WE = HIGH; OE = LOW)
tRAS tRP tRAS
RAS
tCRP tRCD tRSH tCHR
CAS
tAR tASR tRAD tRAH tASC tRAL tCAH
ADDRESS
Row
Column
tAA tRAC tCAC tCLZ tOFF(2)
I/O
Open
tOE tORD
Valid Data
Open
tOD
OE
Don't Care
Notes: 1. A Hidden Refresh may also be performed after a Write Cycle. In this case, WE = LOW and OE = HIGH. 2. tOFF is referenced from rising edge of RAS or CAS, whichever occurs last.
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Integrated Circuit Solution Inc.
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IC41SV4105
ORDERING INFORMATION Commercial Range: 0C to 70C Voltage: 2.2V
Speed (ns) 50 50 50 50 70 70 70 70 100 100 100 100 Order Part No. IC41SV4105-50J IC41SV4105-50T IC41SV4105-50JG IC41SV4105-50TG IC41SV4105-70J IC41SV4105-70T IC41SV4105-70JG IC41SV4105-70TG IC41SV4105-100J IC41SV4105-100T IC41SV4105-100JG IC41SV4105-100TG Package 300mil SOJ 300mil TSOP-2 300mil SOJ Pb-free 300mil TSOP-2 Pb-free 300mil SOJ 300mil TSOP-2 300mil SOJ Pb-free 300mil TSOP-2 Pb-free 300mil SOJ 300mil TSOP-2 300mil SOJ Pb-free 300mil TSOP-2 Pb-free
Integrated Circuit Solution Inc.
HEADQUARTER: NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK, HSIN-CHU, TAIWAN, R.O.C. TEL: 886-3-5780333 Fax: 886-3-5783000 BRANCH OFFICE: 7F, NO. 106, SEC. 1, HSIN-TAI 5TH ROAD, HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C. TEL: 886-2-26962140 FAX: 886-2-26962252 http://www.icsi.com.tw
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